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Differential I/O Termination
SV51006
2014.01.10
Figure 5-16: HSTL I/O Standard Termination
This figure shows the details of HSTL I/O termination on the Stratix V devices. This is not applicable for
HSUL-12 I/O standard.
Termination
HSTL Class I
HSTL Class II
50 Ω
V TT
V TT
50 Ω
50 Ω
V TT
External
On-Board
Termination
50 Ω
VREF
50 Ω
VREF
Transmitter
Series OCT 50 Ω
50 Ω
50 Ω
V TT
Receiver
Transmitter
Series OCT 25 Ω
V TT
50 Ω
50 Ω
50 Ω
V TT
Receiver
OCT Transmit
VREF
VREF
Transmitter
Receiver
Transmitter
Receiver
OCT Receive
50 Ω
V CCIO
100 Ω
FPGA
Parallel OCT
V TT
50 Ω
50 Ω
V CCIO
100 Ω
FPGA
Parallel OCT
VREF
100 Ω
VREF
100 Ω
Transmitter
V CCIO
GND
V CCIO
Receiver
Transmitter
V CCIO
GND
V CCIO
Receiver
Series
OCT 50 Ω
100 Ω
VREF
100 Ω
Series
OCT 25 Ω
100 Ω
VREF
100 Ω
OCT in
50 Ω
50 Ω
Bidirectional
100 Ω
100 Ω
100 Ω
100 Ω
Pins
GND
VREF
GND
Series
OCT 50 Ω
GND
VREF
GND
Series
OCT 25 Ω
FPGA
FPGA
FPGA
FPGA
Related Information
Differential I/O Termination
The I/O pins are organized in pairs to support differential I/O standards. Each I/O pin pair can support
differential input and output buffers.
The supported I/O standards such as Differential SSTL-12, Differential SSTL-15, Differential SSTL-125, and
Differential SSTL-135 typically do not require external board termination.
Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost.
Dynamic OCT reduces the number of external termination resistors used.
Differential HSTL, SSTL, and HSUL Termination
Differential HSTL, SSTL, and HSUL inputs use LVDS differential input buffers with R D support.
Differential HSTL, SSTL, and HSUL outputs are not true differential outputs. These I/O standards use two
single-ended outputs with the second output programmed as inverted.
Altera Corporation
I/O Features in Stratix V Devices
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